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Consultpinnacle
29 Posts |
 Posted - 23 Jan 2004 : 03:50:51
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Hello
We are currently creating a design specification to present digital and analog i/o to the outside world from our product using the AGX.
Questions regarding J40.
Are the following available for use or currently reserved:
Pins 1,3,5,6,9,11,13,15,27,29,31 : Digital IO (Vol 0.5V) (Vih 3.3V)
Pins 17,19,21,23,25 : A/D IO (8-10 bit resolution, input range 0-3.8V)
Pins 32,34,36,38: CPLD GPIO (Vol 0.4V) (Vih 2.4V)
This gives total of 11 Digital Smart I/O, 5 A/D Smart I/O, 4 CPLD GPIO
Also what exactly is a CPLD General Purpose IO???
Section 1.26 of the AGX manual states that:
There are 16 ADSmartIO configurable Digital IO Ports
- Does this include the 5 going through the A/D convertor?
There are 10 Additional GPIOs
-Where are these located?
There are 4/D Inputs
- Where are these located?
I thank you in advance for your help!
Graham Libaert |
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akidder
1519 Posts |
Posted - 23 Jan 2004 : 11:24:40
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Hi Graham. Thanks for your note. I believe someone else has responded to you directly, but here's a response for other interested readers.
A good starting point for answers about AGX I/Os is section 4.6 of the User's Manual. It summarizes the discrete I/Os and gives references of where to get further information.
I'm not sure about the pin references you cited for header J40. Most of the digital I/Os are on J14, with a few more on J8.
For the 16 ADSmartIOs, look for the ROWn and COLn signals on header J14. There are eight of each, which can also be used as general purpose I/Os.
Three of the A/Ds on the AGX are supplied by the ADSmartIO controller. The fourth one is connected to the touch panel controller, and it looks like it's not going to be as useful an input as we expected (among other things, it may interfere with touch panel operation). If I were you, I'd specify the three A/Ds found on J8, pins 13, 15 and 17 for now.
Though not as clearly documented yet, you do have a few more A/Ds available, if you want them. These are ADSmartIO PA0-PA4 and are 0-Vref (2.5V) inputs. You'll have to trade off if you want to use each of these as an A/D or as a digital I/O.
We use CPLDs (complex programmable logic devices) on our systems to provide core logic (e.g. interrupt control, power management, etc). We use some of the I/Os on those parts to provide general purpose I/Os for application use. On the AGX, you can find those signals on J8 and J14.
The ten additional GPIOs come from the Epson graphics controller, if it's installed on your systems. The signals are on J8; electrical specs are in section 6.2.4.
I hope this information helps! |
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akidder
1519 Posts |
Posted - 23 Jan 2004 : 15:05:32
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FYI, Graham responded to this post that the "J40" entry was a typo.
(He and I deleted both postings of an accidental double posting at the same time, so I'm adding back the basics of his post here.) |
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Consultpinnacle
29 Posts |
Posted - 26 Jan 2004 : 05:00:26
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Hello
To confirm then:
In total from J14, I can get (if i were to use PA0 - PA4 as analog):
11 Digital I/O (ROWO-ROW7 & COL5-COL7)
5 Analog I/O (COL0 - COL4)
Which of the A/Ds is connected to the touch panel controller - (is it COL4 or CPLDIO6)?
The other issue i am unsure on is regards to the Voltage range on PA0 to PA4.
Section 6.2.6 of the manual states that the voltage range is up to 10.8 volts, however in your earlier post, you mentioned that they are 0 to Vref 2.5V inputs.
Thanks
Graham
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Edited by - Consultpinnacle on 26 Jan 2004 05:14:48 |
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akidder
1519 Posts |
Posted - 26 Jan 2004 : 18:02:20
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Hi Graham. You are correct that you could configure an 11/5 split between digital I/Os and A/Ds from the ADSmartIO signals available on J14.
If you wanted to add three more A/D inputs, you could use the three ADSmartIOs A/Ds (PA5-PA7/ANIN1-3) on J8. These are always A/Ds because they are connected to voltage dividers.
There are two input voltage ranges among the ADSmartIO A/Ds on the AGX. The voltage range of the ADSmartIO Atmel microcontroller is 0 to Vref; COL0-4 use this input range. PA5-PA7 (ANIN1-3) of the AGX have voltage dividing resistors on them to support higher voltage inputs; their range extends from 0 to about 10.8V.
As for the touch panel controller A/D input , it is ANIN0 and is located at at J8.11. Leave that input out of your specs.
I hope this helps clarify the issues!
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Consultpinnacle
29 Posts |
Posted - 27 Jan 2004 : 05:53:23
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Yes, it does.
My current design brief is to provide minimum of 6 digital I/O and 4 Analogue I/O.
So i can meet that requirement using J14 alone. (keeps it simple!).
I also hope this string provides help for other developers of AGX projects.
Thanks for the help!
Graham |
Edited by - Consultpinnacle on 27 Jan 2004 06:54:18 |
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alkey3
6 Posts |
Posted - 22 Mar 2005 : 15:24:07
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I am looking at using CPLDIO 3-6 on J14 as control signals to an external circuit. Are these I/O defaults set to tri-state?
I assume the information presented here on the AGX is also applicable to the VGX board as well?
Is the example file AGXDigitalIo.exe also applicable to the VGX? |
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