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ctacke
877 Posts |
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kgibson
2 Posts |
 Posted - 17 Jun 2003 : 18:08:04
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I've run the UCBParallel sample program (720020-11501_UCBParallel-2) I've noticed that ports IOB5, IOB1 and IOA5 do not change. I have tried this program on 2 different ADS Graphics Masters and have the same results. I want to be able to read IOA1 through IOA5 and IOB1 through IOB5. Are there any know conflicts?
Here is the first chunk of the debug output:
-------- Begin UCBParallelTest --------
Creating UCB... ok.
setting initial state to 0x3ff... ok.
reading back initial state... 0x3ff
---- 5 minutes left in test ----
W: 0000 0000 0000 0001 R: 0000 0000 0000 0001
W: 0000 0000 0000 0010 R: 0000 0000 0011 0011
W: 0000 0000 0000 0100 R: 0000 0000 0011 0101
W: 0000 0000 0000 1000 R: 0000 0000 0011 1001
W: 0000 0000 0001 0000 R: 0000 0000 0011 0001
W: 0000 0000 0010 0000 R: 0000 0000 0011 0001
W: 0000 0000 0100 0000 R: 0000 0000 0111 0001
W: 0000 0000 1000 0000 R: 0000 0000 1011 0001
W: 0000 0001 0000 0000 R: 0000 0001 0011 0001
W: 0000 0010 0000 0000 R: 0000 0010 0011 0001
W: 0000 0100 0000 0000 R: 0000 0000 0011 0001
W: 0000 1000 0000 0000 R: 0000 0000 0011 0001
W: 0001 0000 0000 0000 R: 0000 0000 0011 0001
W: 0010 0000 0000 0000 R: 0000 0000 0011 0001
W: 0100 0000 0000 0000 R: 0000 0000 0011 0001
W: 1000 0000 0000 0000 R: 0000 0000 0011 0001 |
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ctacke
877 Posts |
Posted - 19 Jun 2003 : 11:05:01
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| I can reproduce similar results here. It turns out that the current driver does not have a mechanism that allows you to read back line states set programmatically. It's an issue of whether the line is currently defined as an input or an output, so the behavior you see above is actually expected. To see if the application is reading/writing properly you must either check the physical lines for output or set the lines for input. |
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kgibson
2 Posts |
Posted - 19 Jun 2003 : 16:49:38
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I've figured out the problem. After checking all of the hardware, I found that it was a software problem, actually a bug in the software. All I had to do was reset "readState" to 0 after each RETAILMSG.
I don't really understand how we should have "expected" the results previously according to the response from "ctacke". At any rate, the issue is solved and I would suggest modifying the code shown below so that it will work properly.
********** Excerpt from UCB TestThread code section **********
while(bRun)
{
// write a test pattern across the entire DWORD
// this includes lines that are set as input and
// non-existing lines to demostrate what happens
// in each case
state = 0;
msk = 0;
for(m = lastbit ; m >= 0 ; m--)
{
for(i = 0 ; i <= m ; i++)
{
state = (1<
// write the value to EIO
if(ucb->Write(state))
{
// read back the current state
ucb->Read(&readState);
// display what we wrote and read
ToBinary(state, writebinary);
ToBinary(readState, readbinary);
RETAILMSG(TRUE, (_T("W: %s R: %s\r\n"), writebinary, readbinary));
// Modification to UCBParallel, Set readState to 0
readState = 0;
}
Sleep(100);
}
msk |= (1<< (i-1));
}
for(m = 0 ; m <= lastbit ; m++)
{
for(i = 0 ; i <= m ; i++)
{
state = (1<<~i) | msk | (1<<(lastbit - (m-i)));
// write the value to EIO
if(ucb->Write(state))
{
// read back the current state
ucb->Read(&readState);
// display what we wrote and read
ToBinary(state, writebinary);
ToBinary(readState, readbinary);
RETAILMSG(TRUE, (_T("W: %s R: %s\r\n"), writebinary, readbinary));
// // Modification to UCBParallel, Set readState to 0
readState = 0;
}
Sleep(100);
}
msk &= (~(1 << (lastbit - i + 1)));
}
********** Debug Output **********
-------- Begin UCBParallelTest --------
Creating UCB... ok.
setting initial state to 0x3ff... ok.
reading back initial state... 0x3ff
---- 5 minutes left in test ----
W: 0000 0000 0000 0001 R: 0000 0000 0000 0001
W: 0000 0000 0000 0010 R: 0000 0000 0000 0010
W: 0000 0000 0000 0100 R: 0000 0000 0000 0100
W: 0000 0000 0000 1000 R: 0000 0000 0000 1000
W: 0000 0000 0001 0000 R: 0000 0000 0001 0000
W: 0000 0000 0010 0000 R: 0000 0000 0010 0000
W: 0000 0000 0100 0000 R: 0000 0000 0100 0000
W: 0000 0000 1000 0000 R: 0000 0000 1000 0000
W: 0000 0001 0000 0000 R: 0000 0001 0000 0000
W: 0000 0010 0000 0000 R: 0000 0010 0000 0000
W: 0000 0100 0000 0000 R: 0000 0000 0000 0000
W: 0000 1000 0000 0000 R: 0000 0000 0000 0000
W: 0001 0000 0000 0000 R: 0000 0000 0000 0000
W: 0010 0000 0000 0000 R: 0000 0000 0000 0000
W: 0100 0000 0000 0000 R: 0000 0000 0000 0000
W: 1000 0000 0000 0000 R: 0000 0000 0000 0000 |
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