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petersherman
2 Posts |
 Posted - 28 May 2003 : 16:47:46
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I am working with a Bitsy board and the Sharp LQ057Q3DC02 TFT-LCD panel (QVGA/5.7"). In preparation to drive another display in an experiment, I have been working to understand the driver/register settings necessary for proper display function, and to update them for the new display. Unfortunately, I have run into a small snag - and I'm finding my calculations don't match measurements. I am trying to establish if I am missing something that may be key to understanding the operation of the LCD controller section, or what other explanation and issues might contribute to the discrepancy.
Here are the specifics:
From the ADSLOAD.HWT file:
0xB0100028 0x00300F0D ; LCCR3
and later the CPU speed is defined at 206 MHz
Specifically looking at the PCD field of the LCCR3 register (bits 7:0) => 0x0D (hex) = 12 (decimal). This should be the "pixel clock divisor" which divides the main CPU clock by a factor in this field to produce the pixel clock. From the SA-1110 spec from Intel:
Pixel Clock Frequency = CCLK/2(PCD+2) => 206 MHz/2(12+2) = 7.357 MHz.
The measurements taken of the pixel clock frequency (measurements by another person), however, set it at 6.67 MHz. The measurements agree with the Sharp LCD panel spec for the pixel clock signaling frequency (6.3 MHz Typ, 7.0 MHz Max; when V/Q = L).
I am aiming for a pixel clock frequency of approximately 4.48 MHz. Using the calculation from the SA-1110 spec from Intel, I would expect to set the PCD value to 21 or 22 (decimal). However, since the equation does not seem to agree with our measurements, I am looking for some help before assuming this is correct.
First off - do our measurements match those that you expect from the Bitsy LCD Pixel Clock? If so, is the processor actually running at 206 MHz, or something slower? Are the equations from Intel correct (and correctly interpreted)? Am I missing any important paramters or concepts?
Thank you very much.
Peter Sherman
Eastman Kodak Company |
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bngo
4 Posts |
Posted - 28 May 2003 : 17:06:50
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Peter,
I think 0D Hex is equal to 13 dec. If you have the value of pixel clock divisor is 0x0D (HEX) = 13(DEC).
Pixel Clock Frequency = CCLK/2(PCD+2) => 206 MHz/2(13+2) = 6.866 MHz.
Your measurement is 6.67 MHz It is very much correct.
If you want the Pixclk is 4.48MHz you can set the PCD= 15 Hex = 21 dec you may get ~4.3MHz.
Brian
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petersherman
2 Posts |
Posted - 29 May 2003 : 08:21:39
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Thank you Brian. Must have had a brain-lapse! You're absolutely correct that 0D (hex) = 13 (dec), and thus calculations and measurments do agree. I feel silly now. Thanks again!
Pete |
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