; 8bpp LQ64343 panel 0x48000001 0x00 ; Miscellaneous Register (Allow access to registers) 0x480001FC 0x00 ; Display Mode Register (Initial value - no displays) 0x48000010 0x00 ; Memory Clock Configuration Register (CLKI 50MHhz) 0x48000014 0x10 ; LCD Pixel Clock Configuration Register (CLKI/2 25MHz) 0x48000018 0x00 ; CRT/TV Pixel Clock Configuration Register (CLKI 50MHz) 0x4800001C 0x02 ; MediaPlug Clock Configuration Register (CLKI2 pixclock on SA1100) 0x4800001E 0x00 ; CPU To Memory Wait State Select Register (no restrictions) 0x48000021 0x02 ; DRAM Refresh Rate Register (setting for 32 to 50MHz) 0x4800002A 0x00 ; DRAM Timings Control Register 0 (setting for 42 to 50Mhz) 0x4800002B 0x01 ; DRAM Timings Control Register 1 (setting for 42 to 50Mhz) 0x48000020 0x80 ; Memory Configuration Register (initialized SDRAM) 0x48000030 0x2D ; Panel Type Register (TFT, 18bit) 0x48000031 0x00 ; MOD Rate Register (D/C Passive only) 0x48000032 0x4F ; LCD Horizontal Display Width Register ( ((0x4F + 1) * 8) = 640 pixels wide) 0x48000034 0x0D ; LCD Horizontal Non-Display Period Register ( ((0x0D + 1) * 8) = 112 pixels) 0x48000035 0x06 ; TFT FPLINE Start Position Register ( ((6 + 5) * 8) = 88 pixels) 0x48000036 0x01 ; TFT FPLINE Pulse Width Register ( ((1 + 1) * 8) = 16 pixels) 0x48000038 0xDF ; LCD Vertical Display Height Register 0 ( (0x01DF + 1) = 480 lines) 0x48000039 0x01 ; LCD Vertical Display Height Register 1 ( (0x01DF + 1) = 480 lines) 0x4800003A 0x37 ; LCD Vertical Non-Display Period Register ( (0x37 + 1) = 56 lines) 0x4800003B 0x15 ; TFT FPFRAME Start Position Register ( (0x15 + 1) = 22 lines) 0x4800003C 0x02 ; TFT FPFRAME Pulse Width Register ( (2 + 1) = 3 lines) 0x48000040 0x03 ; LCD Display Mode Register ( 8 bpp ) 0x48000041 0x01 ; LCD Miscellaneous Register (dithering enabled, dual panel disabled) 0x48000042 0x00 ; LCD Display Start Address Register 0 0x48000043 0x00 ; LCD Display Start Address Register 1 0x48000044 0x00 ; LCD Display Start Address Register 2 0x48000046 0x40 ; LCD Memory Address Offset Register 0 (0x0140 = 320) 0x48000047 0x01 ; LCD Memory Address Offset Register 1 (0x0140 = 320) 0x48000048 0x00 ; LCD Pixel Panning Register 0x4800004a 0x00 ; LCD Display FIFO High Threshold Control Register 0x4800004B 0x00 ; LCD Display FIFO Low Threshold Control Register 0x48000050 0x4F ; CRT/TV Horizontal Display Width Register 0x48000052 0x13 ; CRT/TV Horizontal Non-Display Period Register 0x48000053 0x01 ; CRT/TV HRTC Start Position Register 0x48000054 0x0B ; CRT/TV HRTC Pulse Width Register 0x48000056 0xDF ; CRT/TV Vertical Display Height Register 0 (0x01df + 1 = 480) 0x48000057 0x01 ; CRT/TV Vertical Display Height Register 1 (0x01df + 1 = 480) 0x48000058 0x2B ; CRT/TV Vertical Non-Display Period Register 0x48000059 0x09 ; CRT/TV VRTC Start Position Register 0x4800005A 0x01 ; CRT/TV VRTC Pulse Width Register 0x4800005B 0x10 ; TV Output Control Register 0x48000060 0x85 ; CRT/TV Display Mode Register 0x48000062 0x00 ; CRT/TV Display Start Address Register 0 0x48000063 0x00 ; CRT/TV Display Start Address Register 1 0x48000064 0x00 ; CRT/TV Display Start Address Register 2 0x48000066 0x80 ; CRT/TV Memory Address Offset Register 0 0x48000067 0x02 ; CRT/TV Memory Address Offset Register 1 0x48000068 0x00 ; CRT/TV Pixel Panning Register 0x4800006A 0x00 ; CRT/TV Display FIFO High Threshold Control Register 0x4800006B 0x00 ; CRT/TV Display FIFO Low Threshold Control Register 0x48000070 0x00 ; LCD Ink/Cursor Control Register 0x48000071 0x01 ; LCD Ink/Cursor Start Address Register 0x48000072 0x00 ; LCD Cursor X Position Register 0 0x48000073 0x00 ; LCD Cursor X Position Register 1 0x48000074 0x00 ; LCD Cursor Y Position Register 0 0x48000075 0x00 ; LCD Cursor Y Position Register 1 0x48000076 0x00 ; LCD Ink/Cursor Blue Color 0 Register 0x48000077 0x00 ; LCD Ink/Cursor Green Color 0 Register 0x48000078 0x00 ; LCD Ink/Cursor Red Color 0 Register 0x4800007A 0x1F ; LCD Ink/Cursor Blue Color 1 Register 0x4800007B 0x3F ; LCD Ink/Cursor Green Color 1 Register 0x4800007C 0x1F ; LCD Ink/Cursor Red Color 1 Register 0x4800007E 0x00 ; LCD Ink/Cursor FIFO Threshold Register 0x48000080 0x00 ; CRT/TV Ink/Cursor Control Register 0x48000081 0x01 ; CRT/TV Ink/Cursor Start Address Register 0x48000082 0x00 ; CRT/TV Cursor X Position Register 0 0x48000083 0x00 ; CRT/TV Cursor X Position Register 1 0x48000084 0x00 ; CRT/TV Cursor Y Position Register 0 0x48000085 0x00 ; CRT/TV Cursor Y Position Register 1 0x48000086 0x00 ; CRT/TV Ink/Cursor Blue Color 0 Register 0x48000087 0x00 ; CRT/TV Ink/Cursor Green Color 0 Register 0x48000088 0x00 ; CRT/TV Ink/Cursor Red Color 0 Register 0x4800008A 0x1F ; CRT/TV Ink/Cursor Blue Color 1 Register 0x4800008B 0x3F ; CRT/TV Ink/Cursor Green Color 1 Register 0x4800008C 0x1F ; CRT/TV Ink/Cursor Red Color 1 Register 0x4800008E 0x00 ; CRT/TV Ink/Cursor FIFO Threshold Register 0x48000100 0x00 ; BitBlt Control Register 0 0x48000101 0x00 ; BitBlt Control Register 1 0x48000102 0x00 ; BitBlt ROP Code/Color Expansion Register 0x48000103 0x00 ; BitBlt Operation Register 0x48000104 0x00 ; BitBlt Source Start Address Register 0 0x48000105 0x00 ; BitBlt Source Start Address Register 1 0x48000106 0x00 ; BitBlt Source Start Address Register 2 0x48000108 0x00 ; BitBlt Destination Start Address Register 0 0x48000109 0x00 ; BitBlt Destination Start Address Register 1 0x4800010A 0x00 ; BitBlt Destination Start Address Register 2 0x4800010C 0x00 ; BitBlt Memory Address Offset Register 0 0x4800010D 0x00 ; BitBlt Memory Address Offset Register 1 0x48000110 0x00 ; BitBlt Width Register 0 0x48000111 0x00 ; BitBlt Width Register 1 0x48000112 0x00 ; BitBlt Height Register 0 0x48000113 0x00 ; BitBlt Height Register 1 0x48000114 0x00 ; BitBlt Background Color Register 0 0x48000115 0x00 ; BitBlt Background Color Register 1 0x48000118 0x00 ; BitBlt Foreground Color Register 0 0x48000119 0x00 ; BitBlt Foreground Color Register 1 0x480001E0 0x00 ; Look-Up Table Mode Register 0x480001E2 0x00 ; Look-Up Table Address Register 0x480001F0 0x10 ; Power Save Configuration Register 0x480001F1 0x00 ; Power Save Status Register 0x480001F4 0x00 ; CPU-to-Memory Access Watchdog Timer Register 0x480001FC 0x01 ; Display Mode Register