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esavolle
31 Posts |
 Posted - 01 Feb 2005 : 10:56:18
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Hi,
we used VGX CE 4.20.20.
Are digital ouputs on VGX three-state ouputs (high-level,low-level, high-impedance) ?
I haven't found the answers in vgx documentation.
thanks for your help
eric |
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ctacke
877 Posts |
Posted - 01 Feb 2005 : 11:22:21
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| Which outputs are you using? Many can be placed into a high-z state by setting them as inputs. See the DIO spec for further details. |
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esavolle
31 Posts |
Posted - 01 Feb 2005 : 11:56:49
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We used the port A of smartio as outputs.
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akidder
1519 Posts |
Posted - 01 Feb 2005 : 14:00:41
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| Yes, they can be put into a Hi-Z state. In the VGX user manual, look at the signal "Type" column. Any pin that is a type of IO can be placed in a Hi-Z state. |
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esavolle
31 Posts |
Posted - 03 Feb 2005 : 08:30:55
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So i sum up:
-we have cabled port A of smartio
-we configure each channel of port A as digital ouput with SIOInitDDRA
-we write value with SIOWritePortA
-if i want to place a channel in Hi-Z state, i configure this channel as input with SIOInitDDRA (the other ones as output)
Am i correct ?
One more question : if i write value on port A and one channel is configured as input, is the bit for this channel ignored ?
thanks for help
eric
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akidder
1519 Posts |
Posted - 08 Feb 2005 : 11:59:07
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You are correct. You can place ADSmartIO channels in a hi-Z state as you described.
Important: Even though an AVR I/O pin is configured as an input, it can still be taken out of a hi-Z state if you enable the pull-up pin (for details, see topic 306).
To keep I/O lines in a hi-Z state when writing to the port, write a "0" to all lines that are configured as inputs. |
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