|Using the Watchdog Timer|
The EP9315 includes a conventional watchdog timer that will reboot the processor if the timer isn't re-armed within a set time perions of 250ms. We have implemented access to this timer and offer it with source code in the example below.
The timer comes with a 7-bit Status Storage Register that when set, will persist after a 3 key reset, user reset, or a watchdog. There is also a Control Register to read the cause of the last system non-power-off reset and the current disabled state of the timer. See the comments in the watchdog.h file for details on how to use these functions and the included CE sample application. Of course, you can modify the code to suit your needs.
Theory of Operation
The watchdog timer is a 7-bit counter, with the most significant bit set to trigger the Watchdog Reset. A 256 Hz clock is used to drive the 7-bit counter, so a Watchdog Reset occurs every 250 ms (64 / 256 Hz).
Once the watchdog timer function is enabled, the application must regularly reset (pet) the watchdog timer within the 250ms time frame. Failure to do so will cause the processor to issue a Watchdog Reset Signal, with a reset pulse period of 250ms.
This watchdog class is currently setup to only work with the Sphere Family of ADS boards.
Key APIs UsedWRITE_REGISTER_ULONG
Lines of Code: 342