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Details about CAN on the GC Plus

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akidder

1519 Posts

Posted - 10 Dec 2002 : 12:15:10

CAN Hardware Details

Here are some technical details about how the CAN controller is mapped on the Graphics Client Plus. Address the chip on 32-bit boundaries.

Physical Address : 0x18000000

CAN (82527) is set to 8-bit non-multiplexed mode (MODE 0 & 1 pins are pulled-up).
82527 controller uses a 16MHz clock

SA1110 MSC1 register (chip select 3): 0x66296529

Registers should be accessed with 4 byte-aligned addresses
(ie. StrongARM address line 2 is connected to address line 0 of the 82527):
0x18000000 : Control Register
0x18000004 : Status Regsiter
0x18000008 : CPU interface Register
...

CAN Interrupts

The interrupt line for the CAN chip does not go directly to the CPU. Instead, it goes to a CPLD, which the GC Plus uses as an interrupt controller. The Ethernet, PCMCIA and UCB 1200/touch screen drivers all use this CPLD for interrupt handling.

The software model of this CPLD is that there are registers in the memory space that you can read and set. The register used to enable the CAN interrupt is at 0x1008008 and the CAN interrupt flag register is at 0x1008000. The CAN interrupt is at bit 5 (0x10). Read these registers and bit-wise change the CAN bit to enable and respond to interrupts.

See this topic for more links and information about CAN on ADS products.

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